(1) Field of the Invention
The invention relates to processes for the manufacture of semiconductor devices and more particularly to processes related to formation of vias and contacts in organic insulative layers on semiconductor wafers.
(2) Background of the Invention and Description of Previous Art
Integrated circuits(ICs) are manufactured by first forming discrete semiconductor devices within the surface of silicon wafers. A multi-level metallurgical interconnection network is then formed over the devices contacting their active elements and wiring them together to create the desired circuits. The Wiring layers are formed by first depositing an insulating layer over the discrete devices, patterning and etching contact openings into this layer, and then depositing conductive material into these openings. A conductive layer is then applied over the insulating layer which is patterned and etched to form wiring interconnections between the device contacts thereby creating a first level of basic circuitry. These basic circuits are then further interconnected by utilizing additional wiring levels laid out over additional insulating layers with via pass throughs.
The performance or speed of the integrated circuits is determined in large part by the conductance and capacitance of the metal wiring network. For many years aluminum wiring and silicon oxide inter level dielectric layers have been the norm. As device densities increase and geometries decrease, however, the RC time constraints of the interconnective wiring have become increasingly restrictive to integrated circuit performance. Thus in order to further improve performance, researchers have, in recent years, intensified their search for a metallurgy offering greater conductivity and insulative materials with lower dielectric constants.
Copper is a prominent replacement for aluminum while various organic insulators such as parylene, and arylene ether polymers, have been successfully used as low dielectric constant(low-k) replacements for silicon oxide. Low-k, when applied to insulative layers in integrated circuits, generally refers to a dielectric constant of less than about 3.5 and preferably less than about 2. Porous silica based materials such as siloxanes, aerogels and xerogels have also been implemented as ILD(inter layer dielectric) and IMD (inter-metal dielectric) layers. Fluorinated polyimides offer some improvement in dielectric constant lowering over conventional polyimides.
Low-k organic polymer dielectrics have also found use in packaging materials for integrated circuit chips. Afzali-Ardakami, et.al., U.S. Pat. No. 5,523,148 cites the lowering of dielectric constant and improvement of copper adhesion to fluorinated polycyanurate polymers and fluorinated arylene ether polymers which are impregnated into various reinforcement materials for electronic packaging structures. Preparation methods for fluorinated arylene ether polymers which have dielectric constants between 2.5 and 2.8 and have a low sensitivity to ambient humidity are cited by Mercer, et.al., U.S. Pat. No. 5,115,082. Burgoyne, et.al., U.S. Pat. No. 5,658,994 describe preparation methods for poly(arylene ether)dielectrics Films are spin coated onto silicon wafers and cured. Polymer films designated as PAE-2 and PAE-4, have dielectric constants of 2.41 and 2.42 respectively when measured at 1 MHz.
Many of the low-k dielectric materials, in particular the arylene ether based polymers, for example FLARE.TM. (Allied Signal Inc.) and Lo-K.TM.2000 (Air Products and Chemicals Inc., Allentown, Pa.) exhibit patterning problems because of their low etch rate selectivities with respect to photoresist. These polymer dielectric layer materials require an oxygen based etchant chemistry for effective patterning to form contact or via openings. Etching is done by RIE(reactive ion etching) or by plasma etching. Typically an O.sub.2 /Ar or O.sub.2 /He etchant chemistry is used.
In order to cope with the poor etch rate selectivity of these organic low-k materials, a hardmask is used to etch the polymer layer. A layer of silicon oxide, deposited, by PECVD(plasma enhanced chemical vapor deposition) is applied over the cured polymer layer. A silicon dioxide hardmask is formed by patterning the silicon oxide layer. The SiO.sub.2 hardmask can then be used to pattern the polymer dielectric layer.
Although the O.sub.2 /Ar or O.sub.2 /He etchant chemistry is an effective etchant for the polymer layer, problems with respect to the profile of the openings etched in the polymer layer and the etching behavior of the hardmask are encountered. Under the etching conditions which lead to bowed profiles, the hardmask profile remains essentially vertical. However, by varying the etching conditions to reduce the bowing of etched via openings in the polymer, the hardmask begins to exhibit an angular aspect similar to faceting. This is illustrated in the cross section of FIG. 1 which shows via openings 16 formed in an organic polymer IMD layer 12 to access metal conductors 18 on insulative layer 20. The metal conductors 18 are typically connected to an underlying structure(not shown) through insulating layer 20. A silicon oxide hardmask 14 has been used to etch the openings 16 with an O.sub.2 /Ar plasma in an HDP(high density plasma) etcher. The via openings 16 in the polymer layer 12 have essentially vertical sidewalls but the oxide hardmask 14 has developed a severe angular aspect or facet 19.
The angular faceting of the hardmask is caused by argon sputtering within the HDP etching tool. Faceting of the hardmask 14 causes problems in maintaining pattern integrity as well as inadequate metal removal problems during a subsequent tungsten CMP(chemical mechanical polishing) process step. In quarter micron technology, the spacing between the metal lines 18 becomes small and the degradation of the hardmask 14 causes a high incidence of via shorts. The bowing phenomenon and the hardmask faceting phenomenon work against each other. Thus as the polymer profile bowing is reduced the hardmask faceting increases.
It would therefore be advantageous to remove the residual oxide hardmask after the via has been etched in the organic layer. Unfortunately, the aluminum conductive layer now lies exposed at the base of the via opening and is subject to damage and contamination if an aqueous etchant is used to remove the residual hardmask.
Havermann, U.S. Pat. No. 5,565,384 shows a method for placing a low-k organic insulative layer between conductors and forming a self-aligned via through a silicon oxide insulative layer which lies over the conductors and the organic layer. The silicon oxide layer forms the main body of the IMD layer and thereby also forms the main body of the via opening. It is relatively thick compared to the thickness of the organic layer. The organic layer serves to reduce the capacitance between the conductors on the same level but also acts as an etch stop for the silicon oxide via etch.
Maniar, et.al., U.S. Pat. No. 5,702,981 describes a method of forming a layer of silicon or aluminum nitride over a patterned conductor to act as a via etch stop and to prevent exposure of a vertical edge of the conductor caused by a mis-aligned via over etch. Woo, et.al., U.S. Pat. No. 5,451,543 similarly uses an etch stop layer over a conductor for etching vias of different depths. The etch stop layer, which can be silicon nitride is chosen for its capacity to endure significant over-etch in a shallow via as a deeper via is etched.